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This pass converts cascaded chains of arithmetic and logic cells ($add, $mul, $and, $or, $xor) into balanced binary trees to improve timing performance in hardware synthesis. The optimization uses a breadth-first search approach to identify chains of compatible cells, then recursively constructs balanced trees that reduce the critical path depth. Features: - Supports arithmetic cells: $add, $mul - Supports logic cells: $and, $or, $xor - Command-line options: -arith (arithmetic only), -logic (logic only) - Preserves signed/unsigned semantics - Comprehensive test suite with 30 test cases Original implementation by Akash Levy <akash@silimate.com> for Silimate. Upstreamed from https://github.com/Silimate/yosys |
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