mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-04 05:19:11 +00:00 
			
		
		
		
	Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes). Necessitates also changing single quotes to `.`, i.e match any. For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.
		
			
				
	
	
		
			20 lines
		
	
	
	
		
			335 B
		
	
	
	
		
			Text
		
	
	
	
	
	
			
		
		
	
	
			20 lines
		
	
	
	
		
			335 B
		
	
	
	
		
			Text
		
	
	
	
	
	
read_verilog -sv <<EOF
 | 
						|
module top;
 | 
						|
logic x;
 | 
						|
logic z;
 | 
						|
assign z = 1'b1;
 | 
						|
always_comb begin
 | 
						|
    logic y;
 | 
						|
    case (x)
 | 
						|
    1'b0:
 | 
						|
        y = 1;
 | 
						|
    endcase
 | 
						|
    if (z)
 | 
						|
        x = y;
 | 
						|
    else
 | 
						|
        x = 1'b0;
 | 
						|
end
 | 
						|
endmodule
 | 
						|
EOF
 | 
						|
logger -expect error '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y. from always_comb process' 1
 | 
						|
proc
 |