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42 lines
885 B
Text
42 lines
885 B
Text
# Test lut2mux pass using a directly constructed $lut (avoids frontend/synth differences in test-verific)
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read_rtlil << EOT
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module \top
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wire width 2 input 1 \a
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wire width 1 output 2 \y
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cell $lut \u_lut
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parameter \WIDTH 2
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parameter \LUT 4'0110
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connect \A \a
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connect \Y \y
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end
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end
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EOT
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select -assert-count 1 t:$lut
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# default mode -> gate-level $_MUX_
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design -save gold
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lut2mux
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rename \top \gate
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select -assert-count 3 gate/t:$_MUX_
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select -assert-count 0 gate/t:$mux
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select -assert-count 0 gate/t:$lut
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# -word mode -> word-level $mux
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design -copy-from gold -as top \top
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select -none
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select top
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lut2mux -word
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select -clear
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rename \top \word
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select -assert-count 3 word/t:$mux
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select -assert-count 0 word/t:$_MUX_
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select -assert-count 0 gate/t:$lut
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# equivalence
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equiv_make \gate \word equiv
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hierarchy -top equiv
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equiv_simple
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equiv_induct
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equiv_status -assert
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