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yosys/tests/verilog/issue4402.ys
2026-03-23 15:21:48 -07:00

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# Issue #4402: read_verilog doesn't respect signed keyword
#
# write_verilog was not emitting the signed keyword for port declarations.
! mkdir -p temp
read_verilog <<EOT
module mod (output k, input signed [5:0] wire0);
assign k = (wire0 <= 0);
endmodule
EOT
hierarchy -top mod
write_verilog temp/issue4402_roundtrip.v
# The output port declaration must include the signed keyword.
! grep -q "input signed" temp/issue4402_roundtrip.v