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https://github.com/YosysHQ/yosys
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4b2f977331
This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
95 lines
2 KiB
Verilog
95 lines
2 KiB
Verilog
module GeneratorSigned1(out);
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output wire signed out;
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assign out = 1;
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endmodule
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module GeneratorUnsigned1(out);
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output wire out;
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assign out = 1;
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endmodule
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module GeneratorSigned2(out);
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output wire signed [1:0] out;
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assign out = 2;
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endmodule
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module GeneratorUnsigned2(out);
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output wire [1:0] out;
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assign out = 2;
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endmodule
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module PassThrough(a, b);
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input wire [3:0] a;
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output wire [3:0] b;
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assign b = a;
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endmodule
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module act(o1, o2, o3, o4, o5, o6, o7, o8, o9, yay1, nay1, yay2, nay2);
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output wire [3:0] o1, o2, o3, o4, o5, o6, o7, o8, o9;
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// unsigned constant
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PassThrough pt1(1'b1, o1);
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// unsigned wire
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wire tmp2;
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assign tmp2 = 1'sb1;
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PassThrough pt2(tmp2, o2);
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// signed constant
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PassThrough pt3(1'sb1, o3);
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// signed wire
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wire signed tmp4;
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assign tmp4 = 1'sb1;
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PassThrough pt4(tmp4, o4);
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// signed expressions
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wire signed [1:0] tmp5a = 2'b11;
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wire signed [1:0] tmp5b = 2'b01;
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PassThrough pt5(tmp5a ^ tmp5b, o5);
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wire signed [2:0] tmp6a = 3'b100;
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wire signed [2:0] tmp6b = 3'b001;
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PassThrough pt6(tmp6a ? tmp6a : tmp6b, o6);
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wire signed [2:0] tmp7 = 3'b011;
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PassThrough pt7(~tmp7, o7);
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reg signed [2:0] tmp8 [0:0];
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initial tmp8[0] = 3'b101;
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PassThrough pt8(tmp8[0], o8);
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wire signed [2:0] tmp9a = 3'b100;
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wire signed [1:0] tmp9b = 2'b11;
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PassThrough pt9(0 ? tmp9a : tmp9b, o9);
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output wire [2:0] yay1, nay1;
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GeneratorSigned1 os1(yay1);
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GeneratorUnsigned1 ou1(nay1);
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output wire [2:0] yay2, nay2;
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GeneratorSigned2 os2(yay2);
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GeneratorUnsigned2 ou2(nay2);
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endmodule
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module ref(o1, o2, o3, o4, o5, o6, o7, o8, o9, yay1, nay1, yay2, nay2);
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output wire [3:0] o1, o2, o3, o4, o5, o6, o7, o8, o9;
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assign o1 = 4'b0001;
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assign o2 = 4'b0001;
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assign o3 = 4'b1111;
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assign o4 = 4'b1111;
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assign o5 = 4'b1110;
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assign o6 = 4'b1100;
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assign o7 = 4'b1100;
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assign o8 = 4'b1101;
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assign o9 = 4'b1111;
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output wire [2:0] yay1, nay1;
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assign yay1 = 3'b111;
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assign nay1 = 3'b001;
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output wire [2:0] yay2, nay2;
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assign yay2 = 3'b110;
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assign nay2 = 3'b010;
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endmodule
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