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41 lines
738 B
Verilog
41 lines
738 B
Verilog
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module MyMem #(
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parameter AddrWidth = 4,
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parameter DataWidth = 4) (
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(* gentb_constant = 1 *)
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input Reset_n_i,
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input Clk_i,
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input [AddrWidth-1:0] Addr_i,
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input [DataWidth-1:0] Data_i,
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output reg [DataWidth-1:0] Data_o,
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input WR_i);
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localparam Size = 2**AddrWidth;
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(* mem2reg *)
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reg [DataWidth-1:0] Mem[Size-1:0];
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integer i;
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always @(negedge Reset_n_i or posedge Clk_i)
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begin
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if (!Reset_n_i)
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begin
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Data_o <= 'bx;
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for (i=0; i<Size; i=i+1)
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begin
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Mem[i] <= 0;
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end
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end
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else
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begin
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Data_o <= Mem[Addr_i];
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if (WR_i)
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begin
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Mem[Addr_i] <= Data_i;
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end
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end
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end
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endmodule
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