yosys/tests/various/elab_sys_tasks.ys at 897a625ad829dd2c69c906f1e390eb26bd8dc7de - mirrors/yosys - Libre-Chip.org

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Udi Finkelstein ac10e7d96d Initial implementation of elaboration system tasks

(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.

2019-05-03 03:10:43 +03:00

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read_verilog -sv elab_sys_tasks.sv