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54 lines
1.1 KiB
Verilog
54 lines
1.1 KiB
Verilog
module dff0_test(n1, n1_inv, clk);
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input clk;
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output n1;
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reg n1 = 32'd0;
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output n1_inv;
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always @(posedge clk)
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n1 <= n1_inv;
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assign n1_inv = ~n1;
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endmodule
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module dff1_test(n1, n1_inv, clk);
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input clk;
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(* init = 32'd1 *)
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output n1;
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reg n1 = 32'd1;
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output n1_inv;
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always @(posedge clk)
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n1 <= n1_inv;
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assign n1_inv = ~n1;
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endmodule
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module dff0a_test(n1, n1_inv, clk);
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input clk;
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(* init = 32'd0 *) // Must be consistent with reg initialiser below
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output n1;
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reg n1 = 32'd0;
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output n1_inv;
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always @(posedge clk)
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n1 <= n1_inv;
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assign n1_inv = ~n1;
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endmodule
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module dff1a_test(n1, n1_inv, clk);
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input clk;
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(* init = 32'd1 *) // Must be consistent with reg initialiser below
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output n1;
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reg n1 = 32'd1;
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output n1_inv;
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always @(posedge clk)
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n1 <= n1_inv;
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assign n1_inv = ~n1;
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endmodule
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module dff_test_997 (y, clk, wire4);
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// https://github.com/YosysHQ/yosys/issues/997
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output wire [1:0] y;
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input clk;
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input signed wire4;
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reg [1:0] reg10 = 0;
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always @(posedge clk) begin
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reg10 <= wire4;
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end
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assign y = reg10;
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endmodule
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