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84 lines
2.5 KiB
Verilog
84 lines
2.5 KiB
Verilog
module $__NX_RAM_ (...);
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parameter INIT = 0;
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parameter OPTION_STD_MODE = "NOECC_24kx2";
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parameter PORT_A_WIDTH = 24;
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parameter PORT_B_WIDTH = 24;
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parameter PORT_A_CLK_POL = 1;
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input PORT_A_WR_EN;
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input [15:0] PORT_A_ADDR;
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input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
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wire [24-1:0] A_DATA;
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output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
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parameter PORT_B_CLK_POL = 1;
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input PORT_B_WR_EN;
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input [15:0] PORT_B_ADDR;
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input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
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wire [24-1:0] B_DATA;
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output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
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`include "brams_init.vh"
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localparam raw_config1_val = OPTION_STD_MODE == "NOECC_48kx1" ? 16'b0000000000000000:
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OPTION_STD_MODE == "NOECC_24kx2" ? 16'b0000001001001001:
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OPTION_STD_MODE == "NOECC_16kx3" ? 16'b0000110110110110:
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OPTION_STD_MODE == "NOECC_12kx4" ? 16'b0000010010010010:
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OPTION_STD_MODE == "NOECC_8kx6" ? 16'b0000111111111111:
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OPTION_STD_MODE == "NOECC_6kx8" ? 16'b0000011011011011:
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OPTION_STD_MODE == "NOECC_4kx12" ? 16'b0000100100100100:
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OPTION_STD_MODE == "NOECC_2kx24" ? 16'b0000101101101101:
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16'bx;
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localparam A_REPEAT = 24 / PORT_A_WIDTH;
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localparam B_REPEAT = 24 / PORT_B_WIDTH;
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assign A_DATA = {A_REPEAT{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
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assign B_DATA = {B_REPEAT{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
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NX_RAM_WRAP #(
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.std_mode(OPTION_STD_MODE),
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.mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
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.mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
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.pcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
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.pckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
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.raw_config0(4'b0000),
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.raw_config1(raw_config1_val[15:0]),
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.mem_ctxt($sformatf("%s",bram_init_to_string(INIT,A_REPEAT,PORT_A_WIDTH))),
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) _TECHMAP_REPLACE_ (
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.ACK(PORT_A_CLK),
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//.ACKS(PORT_A_CLK),
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//.ACKD(), // Not used in Non-ECC modes
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//.ACKR(),
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//.AR(),
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//.ACOR(),
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//.AERR(),
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.ACS(PORT_A_CLK_EN),
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.AWE(PORT_A_WR_EN),
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.AA(PORT_A_ADDR),
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.AI(A_DATA),
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.AO(PORT_A_RD_DATA),
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.BCK(PORT_B_CLK),
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//.BCKC(PORT_B_CLK),
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//.BCKD(), // Not used in Non-ECC modes
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//.BCKR()
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//.BR(),
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//.BCOR(),
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//.BERR(),
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.BCS(PORT_B_CLK_EN),
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.BWE(PORT_B_WR_EN),
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.BA(PORT_B_ADDR),
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.BI(B_DATA),
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.BO(PORT_B_RD_DATA)
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);
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endmodule
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