mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 19:52:31 +00:00
5 lines
105 B
Verilog
5 lines
105 B
Verilog
`timescale 1ns/1ps
|
|
|
|
`include "cells_sim_ams.v"
|
|
`include "cells_sim_digital.v"
|
|
`include "cells_sim_wip.v"
|