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yosys/techlibs/common
History
Clifford Wolf c4b8575f43 Add "wreduce -keepdc", fixes #1016 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-20 15:36:13 +02:00
..
.gitignore Added first help messages for cell types 2015-10-14 16:27:42 +02:00
adff2dff.v
cellhelp.py Progress on cell help messages 2015-10-17 02:35:19 +02:00
cells.lib
cmp2lut.v cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
dff2ff.v Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
gate2lut.v gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00
Makefile.inc cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
pmux2mux.v
prep.cc Add "wreduce -keepdc", fixes #1016 2019-05-20 15:36:13 +02:00
simcells.v Fix typo. 2018-12-05 17:13:27 +00:00
simlib.v Improve $specrule interface 2019-04-23 22:57:10 +02:00
synth.cc Run "peepopt" in generic "synth" pass and "synth_ice40" 2019-04-30 08:10:37 +02:00
techmap.v Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00