tux3 88f5977093 SystemVerilog support for implicit named port connections ... This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.		2019-06-06 18:07:49 +02:00
..
.gitignore
const2ast.cc	Added support for unsized constants, fixes #1022	2019-05-27 11:42:10 +02:00
Makefile.inc	Read bigger Verilog files.	2019-05-18 14:20:30 +03:00
preproc.cc
verilog_frontend.cc
verilog_frontend.h
verilog_lexer.l	Merge branch 'master' into wandwor	2019-05-27 19:07:46 +02:00
verilog_parser.y	SystemVerilog support for implicit named port connections	2019-06-06 18:07:49 +02:00