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https://github.com/YosysHQ/yosys
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95 lines
2.2 KiB
Verilog
95 lines
2.2 KiB
Verilog
/*
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ISC License
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Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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wire [47:0] P_48;
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// For pin descriptions, see Section 9 of PolarFire FPGA Macro Library Guide:
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// https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf
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MACC_PA _TECHMAP_REPLACE_ (
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.DOTP(1'b0),
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.SIMD(1'b0),
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.OVFL_CARRYOUT_SEL(1'b0),
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.AL_N(1'b1),
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.A(A),
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.A_BYPASS(1'b1),
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.A_SRST_N(1'b1),
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.A_EN(1'b1),
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.B(B),
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.B_BYPASS(1'b1),
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.B_SRST_N(1'b1),
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.B_EN(1'b1),
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.D(18'b0),
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.D_BYPASS(1'b1),
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.D_ARST_N(1'b1),
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.D_SRST_N(1'b1),
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.D_EN(1'b1),
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.CARRYIN(1'b0),
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.C(48'b0),
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.C_BYPASS(1'b1),
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.C_ARST_N(1'b1),
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.C_SRST_N(1'b1),
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.C_EN(1'b1),
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.P(P_48),
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.P_BYPASS(1'b1),
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.P_SRST_N(1'b1),
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.P_EN(1'b1),
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.PASUB(1'b0),
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.PASUB_BYPASS(1'b1),
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.PASUB_AD_N(1'b0),
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.PASUB_SL_N(1'b1),
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.PASUB_SD_N(1'b0),
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.PASUB_EN(1'b1),
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.CDIN_FDBK_SEL(2'b00),
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.CDIN_FDBK_SEL_BYPASS(1'b1),
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.CDIN_FDBK_SEL_AD_N(2'b00),
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.CDIN_FDBK_SEL_SL_N(1'b1),
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.CDIN_FDBK_SEL_SD_N(2'b00),
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.CDIN_FDBK_SEL_EN(1'b1),
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.ARSHFT17(1'b0),
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.ARSHFT17_BYPASS(1'b1),
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.ARSHFT17_AD_N(1'b0),
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.ARSHFT17_SL_N(1'b1),
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.ARSHFT17_SD_N(1'b0),
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.ARSHFT17_EN(1'b1),
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.SUB(1'b0),
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.SUB_BYPASS(1'b1),
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.SUB_AD_N(1'b0),
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.SUB_SL_N(1'b1),
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.SUB_SD_N(1'b0),
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.SUB_EN(1'b1)
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);
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assign Y = P_48;
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endmodule
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