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33 lines
999 B
Verilog
33 lines
999 B
Verilog
//-----------------------------------------------------
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// Design Name : gray_counter
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// File Name : gray_counter.v
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// Function : 8 bit gray counterS
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module gray_counter (
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out , // counter out
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enable , // enable for counter
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clk , // clock
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rst // active hight reset
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);
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//------------Input Ports--------------
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input clk, rst, enable;
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//----------Output Ports----------------
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output [ 7:0] out;
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//------------Internal Variables--------
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wire [7:0] out;
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reg [7:0] count;
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//-------------Code Starts Here---------
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always @ (posedge clk)
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if (rst)
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count <= 0;
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else if (enable)
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count <= count + 1;
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assign out = { count[7], (count[7] ^ count[6]),(count[6] ^
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count[5]),(count[5] ^ count[4]), (count[4] ^
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count[3]),(count[3] ^ count[2]), (count[2] ^
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count[1]),(count[1] ^ count[0]) };
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endmodule
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