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18 lines
338 B
Verilog
18 lines
338 B
Verilog
module abc9_test027(output reg o);
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initial o = 1'b0;
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always @*
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o <= ~o;
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endmodule
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module abc9_test028(input i, output o);
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wire w;
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unknown u(~i, w);
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unknown2 u2(w, o);
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endmodule
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module abc9_test032(input clk, d, r, output reg q);
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initial q = 1'b0;
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always @(negedge clk or negedge r)
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if (!r) q <= 1'b0;
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else q <= d;
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endmodule
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