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77 lines
3 KiB
C++
77 lines
3 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifdef VERIFIC_LINEFILE_INCLUDES_LOOPS
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#include <stack>
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/*
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This Visitor decorates the AST with a loop ID attribute for all outer for loops.
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All AST nodes contained within the subtree of an outer for-loop
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have the same ID carried as an additional payload of the "linefile" struct.
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The ID is unique accross the flat RTL module set, as it is computed before elaboration.
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It is not unique per instance of the modules.
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A further separation of cells belonging to a given loop instance is necessary by means of
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connectivity analysis.
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No "loop instance" information seems to exist to cluster those loops elements together unfortunately.
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*/
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class DecorateLoopsVisitor : public VeriVisitor
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{
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public:
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DecorateLoopsVisitor() : VeriVisitor() {};
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~DecorateLoopsVisitor() {};
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virtual void VERI_VISIT(VeriLoop, node)
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{
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// std::cout << "Loop in: " << (VeriLoop *)&node << " id: " << outerLoopId << std::endl;
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if (loopStack.empty()) {
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// We increase the loop count when we enter a new set of imbricated loops,
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// That way we have a loop index for the outermost loop as we want to identify and group
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// logic generated by imbricated loops
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outerLoopId = node.Linefile();
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}
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loopStack.push((VeriLoop *)&node);
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}
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void PreAction(VeriTreeNode & /*node*/)
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{
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// VeriNode *vnode = dynamic_cast<VeriNode *>(&node);
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// std::cout << "Node pre: " << vnode << std::endl;
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}
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virtual void PostAction(VeriTreeNode &node)
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{
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// std::cout << "Node post: " << (VeriTreeNode *)&node << std::endl;
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if (loopStack.size()) {
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if (loopStack.top() == (VeriLoop *)&node) {
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loopStack.pop();
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// std::cout << "Loop out: " << (VeriFor *)&node << std::endl;
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return;
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}
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Verific::linefile_type linefile = (Verific::linefile_type)node.Linefile();
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// Unfortunately there is no good way to systematically copy certain AST attributes to the Netlist attributes like:
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// VeriNode *vnode = dynamic_cast<VeriNode *>(&node);
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// vnode->AddAttribute(" in_loop", new VeriIntVal(outerLoopId));
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// Instead using linefile struct to pass that information:
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if (linefile)
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linefile->SetInLoop(outerLoopId);
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}
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}
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private:
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std::stack<VeriLoop *> loopStack;
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linefile_type outerLoopId = nullptr;
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};
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#endif
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