mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 01:54:10 +00:00
26 lines
432 B
Plaintext
26 lines
432 B
Plaintext
read_verilog <<EOT
|
|
module top(input a, output [1:0] b);
|
|
wire c;
|
|
(* submod="bar" *) sub s1(a, c);
|
|
assign b[0] = c;
|
|
endmodule
|
|
|
|
module sub(input a, output c);
|
|
assign c = a;
|
|
endmodule
|
|
EOT
|
|
|
|
hierarchy -top top
|
|
proc
|
|
design -save gold
|
|
|
|
submod
|
|
flatten
|
|
design -stash gate
|
|
|
|
design -import gold -as gold
|
|
design -import gate -as gate
|
|
|
|
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
|
sat -verify -prove-asserts -show-ports miter
|