Marcelina Kościelnicka d3b6b7fe98 xilinx: Fix attributes_test.ys ... This test pretty much passes by accident — the `prep` command runs memory_collect without memory_dff first, which prevents merging read register into the memory, and thus blocks block RAM inference for a reason completely unrelated to the attribute. The attribute setting didn't actually work because it was set on the containing module instead of the actual memory.		2020-10-24 23:52:37 +02:00
..
.gitignore
abc9_dff.ys
add_sub.ys
adffs.ys
attributes_test.ys	xilinx: Fix attributes_test.ys	2020-10-24 23:52:37 +02:00
blockram.ys
bug1460.ys
bug1462.ys
bug1480.ys
bug1598.ys
bug1605.ys
counter.ys
dffs.ys
dsp_abc9.ys	xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)	2020-09-23 09:15:24 -07:00
dsp_cascade.ys
dsp_fastfir.ys
dsp_simd.ys
fsm.ys	synth_xilinx: Use opt_dff.	2020-07-30 22:26:09 +02:00
latches.ys	opt_expr: Remove -clkinv option, make it the default.	2020-07-31 00:08:15 +02:00
logic.ys
lutram.ys
macc.sh
macc.v
macc.ys
macc_tb.v
mul.ys
mul_unsigned.v
mul_unsigned.ys
mux.ys
mux_lut4.ys
nosrl.ys
opt_lut_ins.ys
pmgen_xilinx_srl.ys	satgen: Add support for dffe, sdff, sdffe, sdffce cells.	2020-07-24 03:19:21 +02:00
run-test.sh	tests: Centralize test collection and Makefile generation	2020-09-21 15:07:02 +02:00
shifter.ys
tribuf.sh
tribuf.ys
xilinx_dffopt.ys
xilinx_dffopt_blacklist.txt
xilinx_dsp.ys
xilinx_srl.v
xilinx_srl.ys