Emil J. Tywoniak a5248849d9 WIP		2026-07-20 12:27:17 +02:00
..
achronix
analogdevices
anlogic	WIP	2026-07-20 12:27:17 +02:00
common	WIP	2026-07-20 12:27:17 +02:00
coolrunner2	WIP	2026-07-20 12:27:17 +02:00
easic
efinix	WIP	2026-07-20 12:27:17 +02:00
fabulous	Remove old techmap.	2026-07-08 12:07:58 +02:00
gatemate	WIP	2026-07-20 12:27:17 +02:00
gowin	gowin: replace positional arguments in cells_sim.v with named	2026-07-17 23:33:02 +02:00
greenpak4	WIP	2026-07-20 12:27:17 +02:00
ice40	WIP	2026-07-20 12:27:17 +02:00
intel	Revert "intel: register bram celltypes"	2026-07-17 23:38:01 +02:00
intel_alm	Revert "intel: register bram celltypes"	2026-07-17 23:38:01 +02:00
lattice	WIP	2026-07-20 12:27:17 +02:00
microchip	WIP	2026-07-20 12:27:17 +02:00
nanoxplore	WIP	2026-07-20 12:27:17 +02:00
quicklogic	WIP	2026-07-20 12:27:17 +02:00
sf2
xilinx	WIP	2026-07-20 12:27:17 +02:00
CMakeLists.txt
fix_mod.py