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35 lines
434 B
Verilog
35 lines
434 B
Verilog
module a(Q);
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output wire Q;
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assign Q = 0;
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endmodule
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module b(D);
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input wire D;
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endmodule
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module c;
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wor D;
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assign D = 1;
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assign D = 0;
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assign D = 1;
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assign D = 0;
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wand E;
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wire E_wire = E;
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genvar i;
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for (i = 0; i < 3; i = i + 1)
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begin :genloop
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a a_inst (
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.Q(E)
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);
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b b_inst (
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.D(E_wire)
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);
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end
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endmodule
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