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yosys/backends/verilog
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Xiretza 928fd40c2e Respect \A_SIGNED for $shift 
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
2020-08-18 19:36:24 +02:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc Respect \A_SIGNED for $shift 2020-08-18 19:36:24 +02:00