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https://github.com/YosysHQ/yosys
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99 lines
No EOL
1.7 KiB
Text
99 lines
No EOL
1.7 KiB
Text
##################################################################
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read_verilog -sv -icells <<EOT
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module top(input C, D, E, S, R, output [7:0] Q);
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always @( posedge C, posedge S, posedge R)
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if (R)
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Q[0] <= 0;
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else if (S)
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Q[0] <= 1;
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else
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Q[0] <= D;
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always @( posedge C, posedge S, posedge R)
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if (S)
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Q[1] <= 1;
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else if (R)
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Q[1] <= 0;
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else
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Q[1] <= D;
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always @( posedge C, posedge S, posedge R)
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if (R)
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Q[2] <= 0;
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else if (S)
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Q[2] <= 1;
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else if (E)
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Q[2] <= D;
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always @( posedge C, posedge S, posedge R)
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if (S)
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Q[3] <= 1;
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else if (R)
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Q[3] <= 0;
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else if (E)
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Q[3] <= D;
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assign Q[7:4] = ~Q[3:0];
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endmodule
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EOT
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proc
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opt
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read_liberty dfflibmap_dffsr_s.lib
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copy top top_unmapped
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dfflibmap -liberty dfflibmap_dffsr_s.lib top
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async2sync
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flatten
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opt_clean -purge
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equiv_make top top_unmapped equiv
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equiv_induct equiv
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equiv_status -assert equiv
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##################################################################
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delete top equiv
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copy top_unmapped top
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dfflibmap -liberty dfflibmap_dffsr_r.lib top
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async2sync
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flatten
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opt_clean -purge
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equiv_make top top_unmapped equiv
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equiv_induct equiv
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equiv_status -assert equiv
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##################################################################
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delete top equiv
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copy top_unmapped top
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dfflibmap -liberty dfflibmap_dffsr_mixedpol.lib top
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async2sync
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flatten
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opt_clean -purge
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equiv_make top top_unmapped equiv
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equiv_induct equiv
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equiv_status -assert equiv
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##################################################################
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delete top equiv
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copy top_unmapped top
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dfflibmap -liberty dfflibmap_dffsr_not_next.lib top
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async2sync
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flatten
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opt_clean -purge
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equiv_make top top_unmapped equiv
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equiv_induct equiv
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equiv_status -assert equiv |