mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 09:55:20 +00:00
d53a2bd1d3
The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
17 lines
201 B
Plaintext
17 lines
201 B
Plaintext
bram $__ANLOGIC_DRAM16X4
|
|
init 0
|
|
abits 4
|
|
dbits 2
|
|
groups 2
|
|
ports 1 1
|
|
wrmode 0 1
|
|
enable 0 1
|
|
transp 0 0
|
|
clocks 0 1
|
|
clkpol 0 1
|
|
endbram
|
|
|
|
match $__ANLOGIC_DRAM16X4
|
|
make_outreg
|
|
endmatch
|