Clifford Wolf 17372d8abd Added "abc -luts" option, Improved Xilinx logic mapping		2016-02-01 12:40:32 +01:00
..
tests
.gitignore
arith_map.v
brams.txt	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
brams_bb.v
brams_init.py	Switched to Python 3	2015-08-22 09:59:33 +02:00
brams_map.v	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
cells_map.v
cells_sim.v
drams.txt
drams_bb.v
drams_map.v
Makefile.inc	Switched to Python 3	2015-08-22 09:59:33 +02:00
synth_xilinx.cc	Added "abc -luts" option, Improved Xilinx logic mapping	2016-02-01 12:40:32 +01:00