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https://github.com/YosysHQ/yosys
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89 lines
1.9 KiB
Text
89 lines
1.9 KiB
Text
# Default power of two
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design -reset
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read_rtlil << EOT
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autoidx 3
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attribute \cells_not_processed 1
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attribute \src "<stdin>:1.1-3.10"
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module \top
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attribute \src "<stdin>:2.17-2.20"
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wire width 32 $add$<stdin>:2$1_Y
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attribute \src "<stdin>:2.12-2.21"
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wire width 32 signed $pow$<stdin>:2$2_Y
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attribute \src "<stdin>:1.29-1.30"
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wire width 15 input 1 \a
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attribute \src "<stdin>:1.51-1.52"
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wire width 32 output 2 \b
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attribute \src "<stdin>:2.17-2.20"
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cell $add $add$<stdin>:2$1
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parameter \A_SIGNED 0
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parameter \A_WIDTH 15
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parameter \B_SIGNED 0
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parameter \B_WIDTH 32
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parameter \Y_WIDTH 32
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connect \A \a
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connect \B 2
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connect \Y $add$<stdin>:2$1_Y
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end
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attribute \src "<stdin>:2.12-2.21"
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cell $pow $pow$<stdin>:2$2
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parameter \A_SIGNED 0
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parameter \A_WIDTH 32
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parameter \B_SIGNED 0
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parameter \B_WIDTH 32
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parameter \Y_WIDTH 32
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connect \A 2
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connect \B $add$<stdin>:2$1_Y
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connect \Y $pow$<stdin>:2$2_Y
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end
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connect \b $pow$<stdin>:2$2_Y
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end
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EOT
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select -assert-count 1 t:$pow
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select -assert-none t:$shl
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opt_expr
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select -assert-none t:$pow
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select -assert-count 1 t:$shl
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read_verilog << EOT
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module ref(input wire [14:0] a, output wire [31:0] b);
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assign b = 1 << (a+2);
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endmodule
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EOT
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equiv_make top ref equiv
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select -assert-any -module equiv t:$equiv
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equiv_induct
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equiv_status -assert
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# Other power of 2 value
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design -reset
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read_verilog <<EOT
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module top(input wire [14:0] a, output wire [31:0] b);
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assign b = 128**(a+2);
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endmodule
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EOT
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# Check the cell counts have changed correctly
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select -assert-count 1 t:$pow
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select -assert-none t:$shl
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select -assert-none t:$mul
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opt_expr
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select -assert-none t:$pow
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select -assert-count 1 t:$shl
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select -assert-count 1 t:$mul
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read_verilog <<EOT
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module ref(input wire [14:0] a, output wire [31:0] b);
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assign b = 1 << (7 * (a+2));
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endmodule
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EOT
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equiv_make top ref equiv
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select -assert-any -module equiv t:$equiv
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equiv_induct
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equiv_status -assert
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