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This option allows you to process a design that includes unsupported SVA. Unsupported SVA gets imported as formal cells using 'x inputs and with the `unsupported_sva` attribute set. This allows you to get a complete list of defined properties or to check only a supported subset of properties. To ensure no properties are unintentionally skipped for actual verification, even in cases where `-sva-continue-on-error` is used by default to read and inspect a design, `hierarchy -simcheck` and `hierarchy -smtcheck` (run by SBY) now ensure that no `unsupported_sva` property cells remain in the design. |
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.. | ||
example.sby | ||
example.sv | ||
Makefile.inc | ||
README | ||
verific.cc | ||
verific.h | ||
verificsva.cc |
This directory contains Verific bindings for Yosys. Use Tabby CAD Suite from YosysHQ if you need Yosys+Verific. https://www.yosyshq.com/ Contact YosysHQ at contact@yosyshq.com for free evaluation binaries of Tabby CAD Suite. Verific Features that should be enabled in your Verific library =============================================================== database/DBCompileFlags.h: DB_PRESERVE_INITIAL_VALUE Testing Verific+Yosys+SymbiYosys for formal verification ======================================================== Install Yosys+Verific, SymbiYosys, and Yices2. Install instructions: http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing Then run in the following command in this directory: sby -f example.sby This will generate approximately one page of text output. The last lines should be something like this: SBY [example] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:00 (0) SBY [example] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:00 (0) SBY [example] summary: engine_0 (smtbmc yices) returned PASS for basecase SBY [example] summary: engine_0 (smtbmc yices) returned PASS for induction SBY [example] summary: successful proof by k-induction. SBY [example] DONE (PASS, rc=0)