mirror of
https://github.com/YosysHQ/yosys
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325 lines
6.3 KiB
Verilog
325 lines
6.3 KiB
Verilog
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module gen_test1(clk, a, b, y);
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input clk;
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input [7:0] a, b;
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output reg [7:0] y;
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genvar i, j;
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wire [15:0] tmp1;
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generate
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for (i = 0; i < 8; i = i + 1) begin:gen1
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wire and_wire, or_wire;
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assign and_wire = a[i] & b[i];
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assign or_wire = a[i] | b[i];
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if (i % 2 == 0) begin:gen2true
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assign tmp1[i] = and_wire;
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assign tmp1[i+8] = or_wire;
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end else begin:gen2false
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assign tmp1[i] = or_wire;
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assign tmp1[i+8] = and_wire;
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end
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end
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for (i = 0; i < 8; i = i + 1) begin:gen3
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wire [4:0] tmp2;
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for (j = 0; j <= 4; j = j + 1) begin:gen4
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wire tmpbuf;
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assign tmpbuf = tmp1[i+2*j];
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assign tmp2[j] = tmpbuf;
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end
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always @(posedge clk)
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y[i] <= ^tmp2;
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end
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endgenerate
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endmodule
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// ------------------------------------------
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module gen_test2(clk, a, b, y);
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input clk;
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input [7:0] a, b;
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output reg [8:0] y;
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integer i;
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reg [8:0] carry;
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always @(posedge clk) begin
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carry[0] = 0;
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for (i = 0; i < 8; i = i + 1) begin
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casez ({a[i], b[i], carry[i]})
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3'b?11, 3'b1?1, 3'b11?:
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carry[i+1] = 1;
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default:
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carry[i+1] = 0;
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endcase
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y[i] = a[i] ^ b[i] ^ carry[i];
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end
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y[8] = carry[8];
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end
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endmodule
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// ------------------------------------------
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module gen_test3(a, b, sel, y, z);
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input [3:0] a, b;
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input sel;
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output [3:0] y, z;
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genvar i;
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generate
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for (i=0; i < 2; i=i+1)
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assign y[i] = sel ? a[i] : b[i], z[i] = sel ? b[i] : a[i];
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for (i=0; i < 2; i=i+1) begin
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if (i == 0)
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assign y[2] = sel ? a[2] : b[2];
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else
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assign z[2] = sel ? a[2] : b[2];
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case (i)
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default:
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assign z[3] = sel ? a[3] : b[3];
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0:
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assign y[3] = sel ? a[3] : b[3];
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endcase
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end
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endgenerate
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endmodule
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// ------------------------------------------
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module gen_test4(a, b);
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input [3:0] a;
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output [3:0] b;
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genvar i;
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generate
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for (i=0; i < 3; i=i+1) begin : foo
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localparam PREV = i - 1;
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wire temp;
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if (i == 0)
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assign temp = a[0];
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else
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assign temp = foo[PREV].temp & a[i];
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assign b[i] = temp;
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end
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endgenerate
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endmodule
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// ------------------------------------------
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module gen_test5(input_bits, out);
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parameter WIDTH = 256;
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parameter CHUNK = 4;
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input [WIDTH-1:0] input_bits;
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output out;
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genvar step, i, j;
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generate
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for (step = 1; step <= WIDTH; step = step * CHUNK) begin : steps
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localparam PREV = step / CHUNK;
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localparam DIM = WIDTH / step;
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for (i = 0; i < DIM; i = i + 1) begin : outer
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localparam LAST_START = i * CHUNK;
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for (j = 0; j < CHUNK; j = j + 1) begin : inner
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wire temp;
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if (step == 1)
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assign temp = input_bits[i];
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else if (j == 0)
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assign temp = steps[PREV].outer[LAST_START].val;
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else
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assign temp
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= steps[step].outer[i].inner[j-1].temp
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& steps[PREV].outer[LAST_START + j].val;
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end
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wire val;
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assign val = steps[step].outer[i].inner[CHUNK - 1].temp;
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end
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end
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endgenerate
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assign out = steps[WIDTH].outer[0].val;
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endmodule
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// ------------------------------------------
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module gen_test6(output [3:0] o);
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generate
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genvar i;
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for (i = 3; i >= 0; i = i-1) begin
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assign o[i] = 1'b0;
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end
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endgenerate
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endmodule
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// ------------------------------------------
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module gen_test7;
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reg [2:0] out1;
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reg [2:0] out2;
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wire [2:0] out3;
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generate
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if (1) begin : cond
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reg [2:0] sub_out1;
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reg [2:0] sub_out2;
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wire [2:0] sub_out3;
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initial begin : init
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reg signed [31:0] x;
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x = 2 ** 2;
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out1 = x;
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sub_out1 = x;
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end
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always @* begin : proc
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reg signed [31:0] x;
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x = 2 ** 1;
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out2 = x;
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sub_out2 = x;
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end
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genvar x;
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for (x = 0; x < 3; x = x + 1) begin
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assign out3[x] = 1;
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assign sub_out3[x] = 1;
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end
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end
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endgenerate
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// `define VERIFY
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`ifdef VERIFY
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assert property (out1 == 4);
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assert property (out2 == 2);
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assert property (out3 == 7);
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assert property (cond.sub_out1 == 4);
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assert property (cond.sub_out2 == 2);
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assert property (cond.sub_out3 == 7);
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`endif
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endmodule
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// ------------------------------------------
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module gen_test8;
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// `define VERIFY
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`ifdef VERIFY
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`define ASSERT(expr) assert property (expr);
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`else
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`define ASSERT(expr)
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`endif
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wire [1:0] x = 2'b11;
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generate
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if (1) begin : A
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wire [1:0] x;
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if (1) begin : B
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wire [1:0] x = 2'b00;
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`ASSERT(x == 0)
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`ASSERT(A.x == 2)
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`ASSERT(A.C.x == 1)
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`ASSERT(A.B.x == 0)
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`ASSERT(gen_test8.x == 3)
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`ASSERT(gen_test8.A.x == 2)
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`ASSERT(gen_test8.A.C.x == 1)
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`ASSERT(gen_test8.A.B.x == 0)
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end
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if (1) begin : C
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wire [1:0] x = 2'b01;
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`ASSERT(x == 1)
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`ASSERT(A.x == 2)
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`ASSERT(A.C.x == 1)
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`ASSERT(A.B.x == 0)
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`ASSERT(gen_test8.x == 3)
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`ASSERT(gen_test8.A.x == 2)
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`ASSERT(gen_test8.A.C.x == 1)
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`ASSERT(gen_test8.A.B.x == 0)
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end
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assign x = B.x ^ 2'b11 ^ C.x;
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`ASSERT(x == 2)
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`ASSERT(A.x == 2)
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`ASSERT(A.C.x == 1)
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`ASSERT(A.B.x == 0)
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`ASSERT(gen_test8.x == 3)
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`ASSERT(gen_test8.A.x == 2)
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`ASSERT(gen_test8.A.C.x == 1)
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`ASSERT(gen_test8.A.B.x == 0)
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end
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endgenerate
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`ASSERT(x == 3)
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`ASSERT(A.x == 2)
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`ASSERT(A.C.x == 1)
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`ASSERT(A.B.x == 0)
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`ASSERT(gen_test8.x == 3)
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`ASSERT(gen_test8.A.x == 2)
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`ASSERT(gen_test8.A.C.x == 1)
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`ASSERT(gen_test8.A.B.x == 0)
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endmodule
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// ------------------------------------------
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module gen_test9;
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// `define VERIFY
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`ifdef VERIFY
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`define ASSERT(expr) assert property (expr);
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`else
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`define ASSERT(expr)
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`endif
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wire [1:0] w = 2'b11;
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generate
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begin : A
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wire [1:0] x;
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begin : B
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wire [1:0] y = 2'b00;
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`ASSERT(w == 3)
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`ASSERT(x == 2)
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`ASSERT(y == 0)
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`ASSERT(A.x == 2)
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`ASSERT(A.C.z == 1)
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`ASSERT(A.B.y == 0)
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`ASSERT(gen_test9.w == 3)
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`ASSERT(gen_test9.A.x == 2)
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`ASSERT(gen_test9.A.C.z == 1)
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`ASSERT(gen_test9.A.B.y == 0)
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end
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begin : C
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wire [1:0] z = 2'b01;
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`ASSERT(w == 3)
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`ASSERT(x == 2)
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`ASSERT(z == 1)
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`ASSERT(A.x == 2)
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`ASSERT(A.C.z == 1)
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`ASSERT(A.B.y == 0)
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`ASSERT(gen_test9.w == 3)
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`ASSERT(gen_test9.A.x == 2)
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`ASSERT(gen_test9.A.C.z == 1)
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`ASSERT(gen_test9.A.B.y == 0)
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end
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assign x = B.y ^ 2'b11 ^ C.z;
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`ASSERT(x == 2)
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`ASSERT(A.x == 2)
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`ASSERT(A.C.z == 1)
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`ASSERT(A.B.y == 0)
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`ASSERT(gen_test9.w == 3)
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`ASSERT(gen_test9.A.x == 2)
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`ASSERT(gen_test9.A.C.z == 1)
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`ASSERT(gen_test9.A.B.y == 0)
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end
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endgenerate
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`ASSERT(w == 3)
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`ASSERT(A.x == 2)
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`ASSERT(A.C.z == 1)
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`ASSERT(A.B.y == 0)
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`ASSERT(gen_test9.w == 3)
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`ASSERT(gen_test9.A.x == 2)
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`ASSERT(gen_test9.A.C.z == 1)
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`ASSERT(gen_test9.A.B.y == 0)
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endmodule
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