mirror of
https://github.com/YosysHQ/yosys
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63 lines
2.2 KiB
C++
63 lines
2.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* The Verilog frontend.
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*
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* This frontend is using the AST frontend library (see frontends/ast/).
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* Thus this frontend does not generate RTLIL code directly but creates an
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* AST directly from the Verilog parse tree and then passes this AST to
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* the AST frontend library.
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*
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*/
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#ifndef VERILOG_FRONTEND_H
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#define VERILOG_FRONTEND_H
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#include "kernel/yosys.h"
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#include "frontends/ast/ast.h"
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#include <stdio.h>
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#include <stdint.h>
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YOSYS_NAMESPACE_BEGIN
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namespace VERILOG_FRONTEND
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{
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/* Ephemeral context class */
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struct ConstParser {
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AST::AstSrcLocType loc;
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private:
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void log_maybe_loc_error(std::string msg);
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void log_maybe_loc_warn(std::string msg);
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// divide an arbitrary length decimal number by two and return the rest
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int my_decimal_div_by_two(std::vector<uint8_t> &digits);
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// find the number of significant bits in a binary number (not including the sign bit)
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int my_ilog2(int x);
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// parse a binary, decimal, hexadecimal or octal number with support for special bits ('x', 'z' and '?')
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void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int len_in_bits, int base, char case_type, bool is_unsized);
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public:
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// convert the Verilog code for a constant to an AST node
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std::unique_ptr<AST::AstNode> const2ast(std::string code, char case_type = 0, bool warn_z = false);
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};
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};
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YOSYS_NAMESPACE_END
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#endif
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