Clifford Wolf ba90e08398 Add support for Verific PRIM_SVA_NOT properties		2017-12-10 01:10:03 +01:00
..
ast	Fix error handling for nested always/initial	2017-12-02 18:52:05 +01:00
blif	Increase maximum LUT size in blifparse to 12 bits	2017-09-27 15:27:42 +02:00
ilang
json
liberty
verific	Add support for Verific PRIM_SVA_NOT properties	2017-12-10 01:10:03 +01:00
verilog	Add Verilog "automatic" keyword (ignored in synthesis)	2017-11-23 08:51:38 +01:00