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33 lines
1.4 KiB
Text
33 lines
1.4 KiB
Text
read_verilog mul.v
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design -save read
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hierarchy -top mul_plain
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proc
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equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mul_plain # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_MULT
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select -assert-none t:CC_MULT %% t:* %D
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design -load read
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hierarchy -top mul_signed_async
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proc
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equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mul_signed_async # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_MULT
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select -assert-count 1 t:CC_BUFG
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select -assert-count 28 t:CC_DFF
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select -assert-none t:CC_MULT t:CC_BUFG t:CC_DFF %% t:* %D
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design -load read
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hierarchy -top mul_unsigned_sync
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proc
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equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mul_unsigned_sync # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_MULT
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select -assert-count 1 t:CC_BUFG
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select -assert-max 18 t:CC_LUT4
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select -assert-count 18 t:CC_DFF
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select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT4 t:CC_DFF %% t:* %D
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