Michael Christensen 67d6f3973b Fix use of blif name in synth_xilinx command		2021-04-27 02:29:52 -07:00
..
tests
.gitignore
abc9_model.v
arith_map.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
brams_init.py
cells_map.v	xilinx: Use dfflegalize.	2020-07-09 18:54:23 +02:00
cells_sim.v	xilinx: Add FDRSE_1, FDCPE_1.	2021-01-27 00:32:00 +01:00
cells_xtra.py	xilinx: Add some missing blackbox cells.	2020-12-21 05:34:26 +01:00
cells_xtra.v	xilinx: Add some missing blackbox cells.	2020-12-21 05:34:26 +01:00
ff_map.v	xilinx: Use dfflegalize.	2020-07-09 18:54:23 +02:00
lut4_lutrams.txt
lut6_lutrams.txt
lut_map.v
lutrams_map.v
Makefile.inc	xilinx: Use dfflegalize.	2020-07-09 18:54:23 +02:00
mux_map.v
synth_xilinx.cc	Fix use of blif name in synth_xilinx command	2021-04-27 02:29:52 -07:00
xc2v_brams.txt
xc2v_brams_map.v
xc3s_mult_map.v
xc3sa_brams.txt
xc3sda_brams.txt
xc3sda_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_brams.txt
xc6s_brams_map.v
xc6s_dsp_map.v
xc7_brams_map.v
xc7_dsp_map.v	xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)	2020-09-23 09:15:24 -07:00
xc7_xcu_brams.txt
xcu_brams_map.v
xcu_dsp_map.v
xcup_urams.txt
xcup_urams_map.v
xilinx_dffopt.cc	xilinx_dffopt: Don't crash on missing IS_*_INVERTED.	2021-01-27 00:32:00 +01:00