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https://github.com/YosysHQ/yosys
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65 lines
1.4 KiB
Text
65 lines
1.4 KiB
Text
read_verilog << EOT
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`define WIDTH 5
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module top(input CLK, input [`WIDTH-1:0] D, input RST, output [`WIDTH-1:0] Q_w);
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reg [`WIDTH-1:0] Q;
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assign Q_w = Q;
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always @(posedge CLK, posedge RST)
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if (RST)
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{Q[`WIDTH-1], Q[0]} <= 0;
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else
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Q <= D;
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endmodule // top
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EOT
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proc
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opt
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check -assert
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select -assert-count 1 t:$dffe
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select -assert-count 2 t:$adff
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design -reset
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read_verilog << EOT
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`define WIDTH 9
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module top(input CLK, input [`WIDTH-1:0] D, input RST, input [`WIDTH-1:0] DR, output [`WIDTH-1:0] Q_w);
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reg [`WIDTH-1:0] Q2;
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assign Q_w = Q2;
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always @(posedge CLK, posedge RST)
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if (RST)
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Q2 = { 2'b11, Q2[`WIDTH-3:3], DR[2:1], 1'b 0};
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else
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Q2 <= D;
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endmodule // top
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EOT
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proc
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opt
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check -assert
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select -assert-count 1 t:$dffe
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select -assert-count 2 t:$adff
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select -assert-count 1 t:$aldff
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design -reset
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read_verilog << EOT
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`define WIDTH 4
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module top(input CLK, input [`WIDTH-1:0] D, input RST, input [`WIDTH-1:0] DR, output [`WIDTH-1:0] Q_w, output [`WIDTH-1:0] Q3_w);
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reg [`WIDTH-1:0] Q2;
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reg [`WIDTH-1:0] Q3;
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assign Q_w = Q2;
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assign Q3_w = Q3;
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always @(posedge CLK, posedge RST)
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if (RST)
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{Q2[3:2], Q3[3:2], Q2[1:0],Q3[1:0]} = {Q2[3:1], 2'b11, Q3[2:0]};
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else begin
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Q2 <= D;
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Q3 <= DR;
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end
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endmodule // top
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EOT
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proc
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opt
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check -assert
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select -assert-count 2 t:$dffe
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select -assert-count 2 t:$adff
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select -assert-count 2 t:$aldff
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