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yosys/techlibs/intel
2019-04-11 19:59:03 -05:00
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a10gx
common Changes in GoWin synth commands and ALU primitive support 2018-12-03 20:08:35 -06:00
cyclone10
cycloneiv
cycloneive Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
cyclonev Fixing issues in CycloneV cell sim 2019-04-11 19:59:03 -05:00
max10
Makefile.inc
synth_intel.cc Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00