yosys/tests/fmt/.gitignore at 81d440565290cc27aa6248e7dae3e5e4bf84fac0 - mirrors/yosys - Libre-Chip.org

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whitequark c285880684 fmt: add tests for Verilog round trip of format expressions.

2023-08-11 04:46:52 +02:00

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	`*.log`
	`iverilog-*`
	`yosys-*`