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https://github.com/YosysHQ/yosys
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35 lines
837 B
Python
35 lines
837 B
Python
#!/usr/bin/env python3
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import sys
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sys.path.append("..")
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import gen_tests_makefile
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import subprocess
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from pathlib import Path
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print("Generate FST for sim models")
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for name in Path("tb").rglob("tb*.v"):
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test_name = name.stem
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print(f"Test {test_name}")
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verilog_name = f"{test_name[3:]}.v"
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out_file = Path("tb") / f"{test_name}.out"
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subprocess.run(
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["iverilog", "-o", str(out_file), str(name), verilog_name],
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stdout=subprocess.DEVNULL,
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stderr=subprocess.DEVNULL,
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check=True
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)
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subprocess.run(
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[str(out_file), "-fst"],
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stdout=subprocess.DEVNULL,
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stderr=subprocess.DEVNULL,
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check=True
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)
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gen_tests_makefile.generate(["--yosys-scripts", "--bash", "--yosys-args", "-w 'Yosys has only limited support for tri-state logic at the moment.'" ])
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