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yosys/techlibs/ice40
David Shah 0dd850e655 abc9: Add wire delays to synth_ice40
Signed-off-by: David Shah <dave@ds0.me>
2019-06-26 11:39:44 +01:00
..
tests
.gitignore
abc_hx.box Fix and cleanup ice40 boxes for carry in/out 2019-06-22 14:27:41 -07:00
abc_hx.lut
abc_lp.box Fix and cleanup ice40 boxes for carry in/out 2019-06-22 14:27:41 -07:00
abc_lp.lut
abc_u.box Fix and cleanup ice40 boxes for carry in/out 2019-06-22 14:27:41 -07:00
abc_u.lut
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v
cells_sim.v Fix and cleanup ice40 boxes for carry in/out 2019-06-22 14:27:41 -07:00
ice40_braminit.cc
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc
ice40_unlut.cc Fixed small typo in ice40_unlut help summary 2019-06-19 16:39:46 -04:00
latches_map.v
Makefile.inc
synth_ice40.cc abc9: Add wire delays to synth_ice40 2019-06-26 11:39:44 +01:00