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11 lines
263 B
Verilog
11 lines
263 B
Verilog
module undef_eqx_nex(y);
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output [7:0] y;
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assign y[0] = 0/0;
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assign y[1] = 0/1;
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assign y[2] = 0/0 == 32'bx;
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assign y[3] = 0/0 != 32'bx;
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assign y[4] = 0/0 === 32'bx;
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assign y[5] = 0/0 !== 32'bx;
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assign y[6] = 0/1 === 32'bx;
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assign y[7] = 0/1 !== 32'bx;
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endmodule
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