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17 lines
No EOL
742 B
Text
17 lines
No EOL
742 B
Text
read_verilog <<EOT
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module top(input a, input b, output y);
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assign y = a & b;
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endmodule
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EOT
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hierarchy -check -top top
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proc; opt -fast
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logger -expect warning "Feature 'abc_new' is experimental" 1
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logger -expect warning "Feature 'write_xaiger2' is experimental" 1
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logger -expect warning "Feature 'read_xaiger2' is experimental" 1
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logger -expect log "ABC: .*i/o = +2/ +1" 2
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logger -expect log "ABC: Warning: The network is combinational\." 1
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logger -expect log "ABC: Networks are equivalent\." 1
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logger -expect warning "Wire top\.\$lit[0-9]+ is used but has no driver\." 1
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logger -expect error "Found 1 problems in 'check -assert'" 1
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abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
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check -assert |