Clifford Wolf 3d27c1cc80 Merge pull request #513 from udif/pr_reg_wire_error ... Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)		2018-08-15 13:35:41 +02:00
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asicworld	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
bram	Added support for (single-clock) transparent memories to bram tests	2016-11-01 10:03:13 +01:00
fsm	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
hana	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
memories	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
realmath	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
sat	Allow $size and $bits in verilog mode, actually check test case	2017-09-29 11:56:43 +02:00
share	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
simple	reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files	2018-06-05 18:00:06 +03:00
smv	Progress in SMV back-end	2015-06-19 14:08:46 +02:00
sva	Major redesign of Verific SVA importer	2018-02-27 20:33:15 +01:00
techmap	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
tools	Fixed typo (sikp -> skip)	2018-06-05 22:41:27 +03:00
unit	Build hotfix in tests/unit/Makefile	2016-12-11 10:58:49 +01:00
various	Modified errors into warnings	2018-06-05 18:03:22 +03:00
vloghtb	bugfix in blif front-end	2015-05-18 11:15:49 +02:00