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yosys/tests/techmap
History
Marcelina Kościelnicka 03e28f7ab4 clk2fflogic: Consistently treat async control signals as negative hold. 
This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
2020-07-09 18:12:47 +02:00
..
.gitignore tests/techmap/run-test.sh to cope with *.ys 2019-08-23 11:09:50 -07:00
abc9.ys Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-15 16:42:16 -08:00
aigmap.ys Add quick test 2019-09-30 15:34:04 -07:00
autopurge.ys Hell let's add the original #1381 testcase too 2019-09-20 17:58:51 -07:00
clkbufmap.ys clkbufmap: Add support for inverters in clock path. 2019-11-25 20:40:39 +01:00
cmp2lcu.ys +/cmp2lcu.v to work efficiently for fully/partially constant inputs 2020-04-03 14:28:22 -07:00
dff2dffs.ys Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
dffinit.ys dffinit: Avoid setting init parameter to zero-length value. 2020-04-14 19:52:19 +02:00
dfflegalize_adff.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
dfflegalize_adff_init.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
dfflegalize_adlatch.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
dfflegalize_adlatch_init.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
dfflegalize_dff.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_dff_init.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_dffsr.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_dffsr_init.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
dfflegalize_dlatch.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_dlatch_const.ys dfflegalize: Add special support for const-D latches. 2020-07-09 18:11:32 +02:00
dfflegalize_dlatch_init.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_dlatchsr.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_dlatchsr_init.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_inv.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_mince.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_minsrst.ys dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
dfflegalize_sr.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
dfflegalize_sr_init.ys clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
extractinv.ys Added extractinv pass 2019-09-19 04:02:48 +02:00
iopadmap.ys iopadmap: Fix z assignment to inout port 2020-04-02 18:15:04 +02:00
mem_simple_4x1_cells.v Added tests/techmap/mem_simple_4x1 2014-02-21 12:06:40 +01:00
mem_simple_4x1_map.v Added read-enable to memory model 2015-09-25 12:23:11 +02:00
mem_simple_4x1_runtest.sh Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh 2014-03-11 11:59:58 +01:00
mem_simple_4x1_tb.v Added tests/techmap/mem_simple_4x1 2014-02-21 12:06:40 +01:00
mem_simple_4x1_uut.v Added tests/techmap/mem_simple_4x1 2014-02-21 12:06:40 +01:00
recursive.v Add test 2019-08-20 20:05:16 -07:00
recursive_map.v Add test 2019-08-20 20:05:16 -07:00
recursive_runtest.sh Add test 2019-08-20 20:05:16 -07:00
run-test.sh shiftx2mux: fix select out of bounds 2020-02-05 16:41:09 -08:00
shiftx2mux.ys shiftx2mux: fix select out of bounds 2020-02-05 16:41:09 -08:00
techmap_replace.ys techmap: Fix cell names with _TECHMAP_REPLACE_.* 2020-03-23 11:17:07 +01:00
wireinit.ys Fix _TECHMAP_REMOVEINIT_ handling. 2019-09-27 18:34:12 +02:00
zinit.ys Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00