mirror of
https://github.com/YosysHQ/yosys
synced 2026-05-20 00:49:44 +00:00
34 lines
1.4 KiB
Text
34 lines
1.4 KiB
Text
|
|
read_verilog luttrees.v
|
|
design -save read
|
|
|
|
hierarchy -top luttrees
|
|
proc
|
|
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -nomx4 -nomx8 # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd luttrees # Constrain all select calls below inside the top module
|
|
|
|
select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %%
|
|
select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D
|
|
|
|
design -load read
|
|
|
|
hierarchy -top luttrees
|
|
proc
|
|
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -nomx4 -nomx8 -luttree # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd luttrees # Constrain all select calls below inside the top module
|
|
|
|
select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %%
|
|
select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D
|
|
|
|
design -load read
|
|
|
|
hierarchy -top luttrees
|
|
proc
|
|
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -nomx4 -nomx8 -luttree -abc_new # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd luttrees # Constrain all select calls below inside the top module
|
|
|
|
select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %%
|
|
select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D
|