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33 lines
1.3 KiB
Text
33 lines
1.3 KiB
Text
read_verilog ../common/logic.v
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hierarchy -top top
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proc
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design -save orig
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equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-max 1 t:CC_LUT1
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select -assert-max 6 t:CC_LUT2
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select -assert-max 2 t:CC_LUT4
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select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_LUT4 %% t:* %D
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design -load orig
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equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_LUT1
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select -assert-count 6 t:CC_LUT2
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select -assert-count 2 t:CC_L2T4
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select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 %% t:* %D
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design -load orig
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equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:CC_LUT1
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select -assert-count 6 t:CC_LUT2
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select -assert-count 2 t:CC_L2T4
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select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 %% t:* %D
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