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84 lines
2.7 KiB
Text
84 lines
2.7 KiB
Text
Using yosys with Libero Soc
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===========================
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Yosys does synthesis and therefore could be used instead of Synplify in
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the Libero workflow. You still have to use LiberoSoc for place, route,
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bitsteam generation, timing analysis...
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This is unfortunately not trivial, but this is also not too difficult.
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When you run the Synthesize step, three tools are executed one after the other.
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You'd better to write a simple script, like this one (assuming the top module
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is top):
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----------- run_yosys.sh --------------
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#!/bin/sh
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set -e
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yosys -p 'read_verilog hdl/top.v; synth_sf2; write_verilog -defparam synthesis/top_yosys.v'
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rwnetlist64 --script yosys/rwnetlist.tcl
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echo "##### run g4compile"
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g4compile --script yosys/run_compile.tcl
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libero SCRIPT:run_yosys.tcl
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------------------------------------
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Yosys will do the synthesis and write a netlist in verilog. Then you have
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to call microsemi tools to build the netlist for the P&R tools.
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The first one do a file format conversion. During the normal workflow, the
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tcl file is created in a temporary file. You can use this one:
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------------- tcl/rwnetlist.tcl ---------
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set_device -fam SmartFusion2
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read_verilog \
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-file {../synthesis/top_yosys.v}
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write_adl -file {../designer/top/top.adl}
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----------------------------------------
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Probably, you will have to change the family for Igloo2.
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The second command link the netlists. The tcl script is generated by
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liberoSoc in designer/top/run_compile.tcl. You can use it as it.
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The "Source Files" value could be changed but it looks to have no effect.
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This commands create the .afl file.
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Then you can use the normal flow. This is done by the run_yosys.tcl:
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----------- run_yosys.tcl --------------
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open_project -file {./top.prjx}
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run_tool -name {PLACEROUTE}
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run_tool -name {PROGRAMDEVICE}
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-----------------------------------------
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Using MSS, HPMS or other IPs
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============================
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This works. You'd better to configure CCC (~ the PLL) and the MSS using
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liberoSoc as the configuration bits are not documented.
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Then you have to manually gather the HDL sources generated for the IPs.
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They are in the component subdirectory. Sometimes there are both a _syn and
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a _pre version of the same file. They are for symplify and precision.
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Use only once, the symplify version should be OK. For the MSS, these are the
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blackboxes, so you don't need them.
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SYSRESET and XTLOSC have one fake port. This is handled, provided you use
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the blackbox module declared by Yosys in cell_sim.v. This is OK by default
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too.
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What is missing
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===============
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Always flatten your design (this is the default). Hierarchical designs
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don't work.
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Constraints (SDC files) are not supported by Yosys. Furthermore, due to
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flattening and optimization, nets name may change.
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More testing...
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