Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, ... meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.		2018-10-25 02:37:56 +03:00
..
syntax_err01.v
syntax_err02.v
syntax_err03.v
syntax_err04.v
syntax_err05.v
syntax_err06.v
syntax_err07.v
syntax_err08.v
syntax_err09.v
syntax_err10.v
syntax_err11.v
syntax_err12.v
syntax_err13.v