Miodrag Milanovic e6f7cf3b29 Update tests		2023-06-09 14:41:45 +02:00
..
.gitignore	support file locations containing spaces	2022-08-08 20:30:50 +02:00
add_sub.ys
adffs.ys
bug1597.ys	Reenable existing equiv_opt tests	2022-10-07 16:04:51 +02:00
bug1598.ys
bug1626.ys	Add #1626 testcase	2020-01-12 15:21:26 -08:00
bug1644.il.gz	Add #1644 testcase	2020-01-17 15:57:52 -08:00
bug1644.ys	Add #1644 testcase	2020-01-17 15:57:52 -08:00
bug2061.ys	opt_lut: Allow more than one -dlogic per cell type.	2021-07-29 17:30:07 +02:00
counter.ys	Call equiv_opt with -multiclock and -assert	2019-12-31 18:39:32 -08:00
dffs.ys
dpram.v
dpram.ys
fsm.ys	synth_ice40: Use opt_dff.	2020-07-30 22:26:20 +02:00
ice40_dsp.ys	test: ice40_dsp test to read +/ice40/cells_sim.v for default params	2020-04-22 16:35:35 -07:00
ice40_opt.ys	Fix tests for check in equiv_opt	2022-10-07 16:04:51 +02:00
ice40_wrapcarry.ys	Change attribute search value to specify precise location instead of simple line number.	2020-02-24 02:41:08 +00:00
latches.ys
logic.ys
macc.v
macc.ys
memories.ys	ice40: Use memory_libmap pass.	2022-05-18 17:32:56 +02:00
mul.ys	Fix warnings	2019-12-31 18:40:11 -08:00
mux.ys	allow range for mux test	2020-06-01 13:48:19 +02:00
rom.v	Revert insertion of 'reg', leave note behind	2020-01-01 09:05:46 -08:00
rom.ys	Update tests	2023-06-09 14:41:45 +02:00
run-test.sh	tests: Centralize test collection and Makefile generation	2020-09-21 15:07:02 +02:00
shifter.ys
spram.v	Tests for ram_style = "huge"	2023-02-21 05:23:15 +13:00
spram.ys	Tests for ram_style = "huge"	2023-02-21 05:23:15 +13:00
tribuf.ys