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13 lines
220 B
Text
13 lines
220 B
Text
read_verilog <<EOT
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module top(input clk, output reg [1:0] q);
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wire [1:0] x = 2'b10;
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always @(posedge clk)
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q <= x & 2'b11;
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endmodule
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EOT
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proc
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sim -clock clk -n 1 -w top
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select -assert-count 1 a:init=2'b10 top/q %i
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