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			82 lines
		
	
	
	
		
			1.7 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			82 lines
		
	
	
	
		
			1.7 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
| 
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| // test taken from systemcaes from iwls2005
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| 
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| module subbytes_00(clk, reset, start_i, decrypt_i, data_i, ready_o, data_o, sbox_data_o, sbox_data_i, sbox_decrypt_o);
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| 
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| input clk;
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| input reset;
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| input start_i;
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| input decrypt_i;
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| input [31:0] data_i;
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| output ready_o;
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| output [31:0] data_o;
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| output [7:0] sbox_data_o;
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| input [7:0] sbox_data_i;
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| output sbox_decrypt_o;
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| 
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| reg ready_o;
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| reg [31:0] data_o;
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| reg [7:0] sbox_data_o;
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| reg sbox_decrypt_o;
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| 
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| reg [1:0] state;
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| reg [1:0] next_state;
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| reg [31:0] data_reg;
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| reg [31:0] next_data_reg;
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| reg next_ready_o;
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| 
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| always @(posedge clk or negedge reset)
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| begin
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| 	if (!reset) begin
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| 		data_reg = 0;
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| 		state = 0;
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| 		ready_o = 0;
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| 	end else begin
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| 		data_reg = next_data_reg;
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| 		state = next_state;
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| 		ready_o = next_ready_o;
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| 	end
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| end
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| 
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| reg [31:0] data_i_var, data_reg_128;
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| reg [7:0] data_array [3:0];
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| reg [7:0] data_reg_var [3:0];
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| 
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| always @(decrypt_i or start_i or state or data_i or sbox_data_i or data_reg)
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| begin
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| 	data_i_var = data_i;
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| 
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| 	data_array[0] = data_i_var[ 31: 24];
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| 	data_array[1] = data_i_var[ 23: 16];
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| 	data_array[2] = data_i_var[ 15:  8];
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| 	data_array[3] = data_i_var[  7:  0];
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| 
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| 	data_reg_var[0] = data_reg[ 31: 24];
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| 	data_reg_var[1] = data_reg[ 23: 16];
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| 	data_reg_var[2] = data_reg[ 15:  8];
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| 	data_reg_var[3] = data_reg[  7:  0];
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| 
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| 	sbox_decrypt_o = decrypt_i;
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| 	sbox_data_o = data_array[state];
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| 	next_state = state;
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| 	next_data_reg = data_reg;
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| 
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| 	next_ready_o = 0;
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| 	data_o = data_reg;
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| 
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| 	if (state) begin
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| 		if (start_i) begin
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| 			next_state = 1;
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| 		end
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| 	end else begin
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| 		data_reg_var[state] = sbox_data_i;
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| 		data_reg_128[ 31: 24] = data_reg_var[0];
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| 		data_reg_128[ 23: 16] = data_reg_var[1];
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| 		data_reg_128[ 15:  8] = data_reg_var[2];
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| 		data_reg_128[  7:  0] = data_reg_var[3];
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| 		next_data_reg = data_reg_128;
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| 		next_state = state + 1;
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| 	end
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| end
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| 
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| endmodule
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