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88 lines
975 B
Verilog
88 lines
975 B
Verilog
module ifdef_1_top(o1, o2, o3, o4);
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`define FAIL input wire not_a_port;
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`ifdef COND_1
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`FAIL
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`elsif COND_2
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`FAIL
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`elsif COND_3
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`FAIL
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`elsif COND_4
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`FAIL
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`else
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`define COND_4
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output wire o4;
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`ifdef COND_1
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`FAIL
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`elsif COND_2
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`FAIL
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`elsif COND_3
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`FAIL
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`elsif COND_4
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`define COND_3
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output wire o3;
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`ifdef COND_1
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`FAIL
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`elsif COND_2
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`FAIL
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`elsif COND_3
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`define COND_2
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output wire o2;
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`ifdef COND_1
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`FAIL
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`elsif COND_2
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`define COND_1
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output wire o1;
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`ifdef COND_1
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`ifdef COND_1
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`elsif COND_2
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`FAIL
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`elsif COND_3
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`FAIL
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`elsif COND_4
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`FAIL
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`else
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`FAIL
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`endif
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`elsif COND_2
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`FAIL
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`elsif COND_3
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`FAIL
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`elsif COND_4
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`FAIL
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`else
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`FAIL
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`endif
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`elsif COND_3
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`FAIL
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`elsif COND_4
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`FAIL
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`else
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`FAIL
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`endif
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`elsif COND_4
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`FAIL
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`else
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`FAIL
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`endif
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`else
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`FAIL
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`endif
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`endif
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endmodule
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