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https://github.com/YosysHQ/yosys
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2a3720921c
For these primitives, Gowin decided to use a different option for describing ports—directly in the module header, i.e. ``` verilog module ADC(input CLK); ``` instead of ``` verilog module ADC(CLK); input CLK; ``` Since this one-time parser becomes too confusing, it is easier to simply add ADC descriptions as they are from a separate file, especially since these primitives are only available in the GW5A series. Test: ``` shell yosys -p "read_verilog top.v; synth_gowin -json top-synth.json -family gw5a" ``` The old version of Yosys simply won't compile the design due to the lack of port descriptions, while the new version will compile without errors. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
260 lines
14 KiB
Verilog
260 lines
14 KiB
Verilog
/********ADC***********/
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//ADC for LRC,GW5AT-138K
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module ADCLRC (
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//Voltage signal source, /mV
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input ADCINBK2A, //input from bank2 IO, adc_in_b is the reference
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input ADCINBK2B, //input from bank2 IO, adc_in_b is the reference
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input ADCINBK3A, //input from bank3 IO, adc_in_b is the reference
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input ADCINBK3B, //input from bank3 IO, adc_in_b is the reference
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input ADCINBK4A, //input from bank4 IO, adc_in_b is the reference
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input ADCINBK4B, //input from bank4 IO, adc_in_b is the reference
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input ADCINBK5A, //input from bank5 IO, adc_in_b is the reference
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input ADCINBK5B, //input from bank5 IO, adc_in_b is the reference
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//control signal
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input [2:0] VSENCTL, //Input source selection (ciu), from 0 to 7: adcv, adct, vdd09_0, vdd09_1, vdd18_0, vdd18_1, vdd33_0, vdd33_1
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input [9:0] FSCAL_VALUE, // temperature mode 510~948, typical value 730; Voltage mode 452~840, typical value 653
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input [11:0] OFFSET_VALUE, //signed number, temperature mode - 1560~- 760, typical value - 1180; Voltage mode - 410~410, typical value 0
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input ADCEN, //Enable signal, active high
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input CLK, //clk input，1/2 shared
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input DRSTN, //0/1 shared, Digital part reset signal, active low
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input ADCREQI, //Measurement request signal, valid rising edge, asynchronous signal
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//output
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output ADCRDY, //The measurement completion signal, active high
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output [13:0] ADCVALUE //The measurement result output, signed number. In voltage mode,/2048 is the actual measured value; In temperature mode,/4 is the actual measured value
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);
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parameter DYN_BKEN = "FALSE";//"FALSE","TRUE"."TRUE",BUF_BK2_EN[0]&BUF_BK3_EN[0]=1
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//Input source selection，1/2 shared
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parameter BUF_SERDES_Q1_EN = 3'b000; //[1:0] does not support "11"
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parameter BUF_BK2_EN = 6'b000000; //[3:0] Only one bit can be 1 at the same time
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parameter BUF_BK3_EN = 6'b000000; //[3:0] Only one bit can be 1 at the same time
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parameter BUF_BK4_EN = 6'b000000; //[3:0] Only one bit can be 1 at the same time
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parameter BUF_BK5_EN = 6'b000000; //[3:0] Only one bit can be 1 at the same time
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parameter BUF_BK10_EN = 5'b00000; //[3:1] Only one bit can be 1 at the same time
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parameter BUF_BK11_EN = 5'b00000; //[3:1] Only one bit can be 1 at the same time
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//Analog terminal option
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parameter CLK_SEL = 1'b0; //Clock source selection. 0,PIOCLK_SEL，1,ciu_clk
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parameter PIOCLK_SEL = 1'b0; //Clock source selection. 1/2 shared，0,mck_adc_clk_osc，1,io_clk
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parameter VSEN_CTL = 3'b000; //Input source selection
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parameter VSEN_CTL_SEL = 1'b0; //vsen_ctl source selection，0,VSEN_CTL，1,ciu_vsen_ctl
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parameter ADC_MODE = 1'b0; //Mode selection
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parameter DIV_CTL = 2'd0; //clock division，0:/1，1:/2，2:/4，3:/8，Clock after frequency division, 500kHz~8MHz
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//Digital terminal options
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parameter SAMPLE_CNT_SEL = 3'd4; //total samples configuration, 0~4:64, 128, 256, 512, 1024 sampling points, and the other values are 2048 sampling points.The total number of samples shall be greater than 7 * sampling period, i.e. SAMPLR_CNT_SEL >= RATE_CHANGE_CTRL-1
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parameter RATE_CHANGE_CTRL = 3'd4; //Sampling period configuration, 0~4:4、8、16、32、64，other values are 128
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endmodule
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//ADCULC,GW5AT-138K
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module ADCULC (
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//Voltage signal source, /mV
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input ADCINBK6A, //input from bank6 IO, adc_in_b is the reference
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input ADCINBK6B, //input from bank6 IO, adc_in_b is the reference
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input ADCINBK7A, //input from bank7 IO, adc_in_b is the reference
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input ADCINBK7B, //input from bank7 IO, adc_in_b is the reference
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//control signal
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input [2:0] VSENCTL, //Input source selection(cib)，0~7: vtest, vdd09_0, vdd09_1, vdd09_2, vdd18_0, vdd18_1, reserved, vdd33
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input [9:0] FSCAL_VALUE, // temperature mode 510~948, typical value 730; Voltage mode 452~840, typical value 653
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input [11:0] OFFSET_VALUE, //signed number, temperature mode - 1560~- 760, typical value - 1180; Voltage mode - 410~410, typical value 0
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input ADCEN, //Enable signal, active high
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input CLK, //clk input
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input DRSTN, //0/1 shared, Digital part reset signal, active low
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input ADCREQI, //Measurement request signal, valid rising edge, asynchronous signal
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output ADCRDY, //The measurement completion signal, active high
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output [13:0] ADCVALUE //The measurement result output, signed number. In voltage mode,/2048 is the actual measured value; In temperature mode,/4 is the actual measured value
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);
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parameter DYN_BKEN = "FALSE";//"FALSE","TRUE"."TRUE",BUF_BK6_EN[0]&BUF_BK7_EN[0]=1
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//Input source selection
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parameter BUF_VCC_EN = 1'b0; //ulc
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parameter BUF_VCCM_EN = 1'b0; //ulc
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parameter BUF_MIPI_M0_EN = 3'b000; //ulc,[1:0] Only one bit can be 1 at the same time
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parameter BUF_MIPI_M1_EN = 3'b000; //ulc,[1:0] Only one bit can be 1 at the same time
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parameter BUF_SERDES_Q0_EN = 3'b000; //ulc,[1:0] Only one bit can be 1 at the same time
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parameter BUF_BK6_EN = 6'b000000; //bk6,[3:0] Only one bit can be 1 at the same time
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parameter BUF_BK7_EN = 6'b000000; //bk7,[3:0] Only one bit can be 1 at the same time
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//Analog terminal option
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parameter CLK_SEL = 1'b0; //Clock source selection. 0,PIOCLK_SEL，1,ciu_clk
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parameter PIOCLK_SEL = 1'b0; //Clock source selection. 1/2 shared，0,mck_adc_clk_osc，1,io_clk
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parameter VSEN_CTL = 3'b000; //Input source selection
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parameter VSEN_CTL_SEL = 1'b0; //vsen_ctl source selection，0,VSEN_CTL，1,ciu_vsen_ctl
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parameter ADC_MODE = 1'b0; //Mode selection
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parameter DIV_CTL = 2'd0; //clock division，0:/1，1:/2，2:/4，3:/8，Clock after frequency division, 500kHz~8MHz
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//Digital terminal options
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parameter SAMPLE_CNT_SEL = 3'd4; //total samples configuration, 0~4:64, 128, 256, 512, 1024 sampling points, and the other values are 2048 sampling points.The total number of samples shall be greater than 7 * sampling period, i.e. SAMPLR_CNT_SEL >= RATE_CHANGE_CTRL-1
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parameter RATE_CHANGE_CTRL = 3'd4; //Sampling period configuration, 0~4:4、8、16、32、64，other values are 128
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endmodule
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//ADC,GW5A-25
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module ADC (
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//control signal
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input CLK, //clk input
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input [2:0] VSENCTL, //Input source selection (ciu), from 0 to 7: glo_left,glo_right,loc_left,vtest,vcc_rt,vccc_rt,vccm_rt,vccx_buf
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input ADCMODE, //Mode selection,0:temperature mode，1:voltage mode
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input DRSTN, //Digital part reset signal, active low
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input ADCREQI, //Measurement request signal, valid rising edge, asynchronous signal
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output ADCRDY, //The measurement completion signal, active high
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output [13:0] ADCVALUE, //The measurement result output, signed number. In voltage mode,/2048 is the actual measured value; In temperature mode,/4 is the actual measured value
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//mdrp
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input MDRP_CLK, //mdrp clock
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input [7:0] MDRP_WDATA, //mdrp write data
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input MDRP_A_INC, //mdrp self-increased address
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input [1:0] MDRP_OPCODE, //mdrp opcode
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output [7:0] MDRP_RDATA, //mdrp read data
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input ADCEN //Enable signal, active high
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);
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//Analog terminal option
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parameter CLK_SEL = 1'b0; //时钟源选择，0:osc(2.5MHz)，1:CLK
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parameter DIV_CTL = 2'd0; //clock division，0:/1，1:/2，2:/4，3:/8，Clock after frequency division, 500kHz~8MHz
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//Input source selection
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parameter BUF_EN = 12'b000000000000; //
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parameter BUF_BK0_VREF_EN = 1'b0; //
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parameter BUF_BK1_VREF_EN = 1'b0; //
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parameter BUF_BK2_VREF_EN = 1'b0; //
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parameter BUF_BK3_VREF_EN = 1'b0; //
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parameter BUF_BK4_VREF_EN = 1'b0; //
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parameter BUF_BK5_VREF_EN = 1'b0; //
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parameter BUF_BK6_VREF_EN = 1'b0; //
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parameter BUF_BK7_VREF_EN = 1'b0; //
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//Digital terminal options
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parameter CSR_ADC_MODE = 1'b1; // Mode selection
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parameter CSR_VSEN_CTRL = 3'd0; // signal source:vccx/vccio_*/vcc_reg -> 7, signal source:vcc_ext -> 4, others -> 0
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parameter CSR_SAMPLE_CNT_SEL = 3'd4; // total samples configuration, 0~4:64, 128, 256, 512, 1024 sampling points, and the other values are 2048 sampling points.The total number of samples shall be greater than 7 * sampling period, i.e. SAMPLR_CNT_SEL >= RATE_CHANGE_CTRL-1
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parameter CSR_RATE_CHANGE_CTRL = 3'd4; // Sampling period configuration, 0~4:4、8、16、32、64，other values are 128
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parameter CSR_FSCAL = 10'd730; // Parameter 1: temperature mode 510~948, typical value 730; Voltage mode 452~840, typical value 653
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parameter CSR_OFFSET = -12'd1180; // Parameter 2, signed number, temperature mode - 1560~- 760, typical value - 1180; Voltage mode - 410~410, typical value 0
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endmodule
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//ADC_SAR,integrated saradc and adc functions.
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module ADC_SAR (
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//`ifdef ADC
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input ADCMODE, //Mode selection
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input [2:0] VSENCTL, //Input source selection
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input CLK, //clk input
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//Digital
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output ADCENO, //Enable signal, active high
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input DRSTN, //Digital part reset signal, active low
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input ADCREQI, //Measurement request signal
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output ADCRDY, //The measurement completion signal, active high
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output [13:0] ADCVALUE, //The measurement result output
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input MDRP_CLK, //mdrp clock
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input [7:0] MDRP_WDATA, //mdrp write data
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input MDRP_A_INC, //mdrp self-increased address
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input [1:0] MDRP_OPCODE,//mdrp opcode
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output [7:0] MDRP_RDATA, //mdrp read data
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//Analog
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output ADC1BIT, //Analog data output
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output ADCCLKO, //Analog clock output
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input ADCENI, //fabric adc enable input
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//`endif
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// SAR
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//`ifdef SARADC
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output [12:0] ADCBIT, //Measurement result output
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output CLKO, //output clk
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output EOC, //The measurement completion signal
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input CLKI, //fabric input clk
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input [6:0] CHEN, //channel select
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input RSTN, //resetn,active low
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input SOC //Measurement request signal
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//`endif
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);
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parameter BUF_EN = 29'b0; // signal source selecor switch
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// Δ-Σ
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//`ifdef ADC
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parameter CLK_SEL = 1'b1; // clk source select
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parameter DIV_CTL = 2'd0; // clock division.0:/1,1:/2,2:/4,3:/8
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parameter ADC_EN_SEL = 1'b0; // adc_en source select
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parameter PHASE_SEL = 1'b0; // adc internal data phase select
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//Digital terminal options
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parameter CSR_ADC_MODE = 1'b1; // Mode selection
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parameter CSR_VSEN_CTRL = 3'd0; // signal source:vccx/vccio_*/vcc_reg -> 7, signal source:vcc_ext -> 4, others -> 0
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parameter CSR_SAMPLE_CNT_SEL = 3'd4; // total samples configuration, 0~4:64, 128, 256, 512, 1024 sampling points, and the other values are 2048 sampling points.The total number of samples shall be greater than 7 * sampling period, i.e. SAMPLR_CNT_SEL >= RATE_CHANGE_CTRL-1
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parameter CSR_RATE_CHANGE_CTRL = 3'd4; // Sampling period configuration, 0~4:4、8、16、32、64，other values are 128
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parameter CSR_FSCAL = 10'd730; // Parameter 1: temperature mode 510~948, typical value 730; Voltage mode 452~840, typical value 653
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parameter CSR_OFFSET = -12'd1180; // Parameter 2, signed number, temperature mode - 1560~- 760, typical value - 1180; Voltage mode - 410~410, typical value 0
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//`endif
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// SAR
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//`ifdef SARADC
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parameter ADC_CLK_DIV = 2'b00; // clock division.00:/1,01:/2,10:/4,11:/8
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parameter ADC_CLKDIV_EN = 1'b0; // clock division enable
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parameter CLK_SRC_SEL = 1'b1; // source clock sel
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parameter VREF_BUF_EN = 1'b1; // BGR vref buffer enable
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parameter COUNT_LEN = 5'b10100; // ADC counter length
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parameter DAC_SAMPLE_END = 5'b10010; // DAC sample end point
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parameter DAC_SAMPLE_START = 5'b01101; // DAC sample start point
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parameter SH_SAMPLE_END = 5'b01011; // SH sample start point
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parameter SH_SAMPLE_START = 5'b00001; // SH sample end point
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parameter AUTO_CHOP_EN = 1'b0; // auto chop
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parameter CHOP_CLK_DIV = 4'b0; // chop clock divider
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//`endif
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endmodule
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//ADCA,15k
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module ADCA (
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// analog
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input ADCMODE, //Mode selection
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input [2:0] VSENCTL, //Input source selection 0-7: vglo_left, vglo_right, vcc2, vccc3, vccb4, vcc5, vccm6, vccc7
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input CLK, //clk input
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input ADCENI, //fabric adc enable input
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input PWRON_DYN, //power enable. 1:on 0:off
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// digital
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input DRSTN, //Digital part reset signal, active low
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input ADCREQI, //Measurement request signal
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output ADCRDY, //The measurement completion signal, active high
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output [13:0] ADCVALUE, //The measurement result output
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input MDRP_CLK, //mdrp clock
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input [7:0] MDRP_WDATA, //mdrp write data
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input MDRP_A_INC, //mdrp self-increased address
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input [1:0] MDRP_OPCODE,//mdrp opcode
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output [7:0] MDRP_RDATA //mdrp read data
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);
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parameter BUF_EN = 20'b0; // signal source selecor switch //[8:0] one-hot; [19:15] one-hot. BUF_EN[6] must be 0
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parameter CLK_SEL = 1'b1; // clk source select
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parameter DIV_CTL = 2'd0; // clock division
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parameter ADC_EN_SEL = 1'b0; // adc_en source select
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parameter PHASE_SEL = 1'b0; // adc internal data phase select
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parameter PWRON_SEL = 1'b0; // power enbale source select. 0:PWRON 1:PWRON_DYN
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parameter PWRON = 1'b1; // as PWRON_DYN
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parameter LDO_MODE = 1'b0; // LDO mode 0:on(2.5/3.3V) 1:off(1.8V)
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//Digital terminal options
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parameter CSR_ADC_MODE = 1'b1; // Mode selection
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parameter CSR_VSEN_CTRL = 3'd0; // signal source:vccx/vccio_*/vcc_reg -> 7, signal source:vcc_ext -> 4, others -> 0
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parameter CSR_SAMPLE_CNT_SEL = 3'd4; // total samples configuration, 0~4:64, 128, 256, 512, 1024 sampling points, and the other values are 2048 sampling points.The total number of samples shall be greater than 7 * sampling period, i.e. SAMPLR_CNT_SEL >= RATE_CHANGE_CTRL-1
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parameter CSR_RATE_CHANGE_CTRL = 3'd4; // Sampling period configuration, 0~4:4、8、16、32、64，other values are 128
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parameter CSR_FSCAL = 10'd730; // Parameter 1: temperature mode 510~948, typical value 730; Voltage mode 452~840, typical value 653
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parameter CSR_OFFSET = -12'd1180; // Parameter 2, signed number, temperature mode - 1560~- 760, typical value - 1180; Voltage mode - 410~410, typical value 0
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endmodule
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