mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-26 10:35:38 +00:00
5 lines
72 B
Verilog
5 lines
72 B
Verilog
module test(input [7:0] in, output out);
|
|
|
|
assign out = ~^in;
|
|
|
|
endmodule
|